The number of memory elements or bits contained within a DRAM has been increasing and will continue to steadily increase with each incremental improvement in both the process manufacturing and the design. As the number of memory bits increases, the need to increase the bit density increases in order to minimize both die area of the DRAM and memory bit access time. A common method of increasing bit density in a DRAM is to reduce the transistor dimensions of both the memory bit and the associated control logic, and to reduce the interconnect dimensions. Reductions in process dimensions are generally accomplished by improvements in both semiconductor process manufacturing and semiconductor mask generating techniques. Another common method of increasing the density of the memory bits within a DRAM is through the use of a vertical process manufacturing technique, or vertical integration. Two common cell structures which use vertical integration techniques are a stacked-capacitor cell and a trench-capacitor cell. These two cell structures allow a charge storage device within a DRAM memory bit cell to occupy the least amount of planar area possible, thus providing a high density of memory bits. Vertical integration techniques allow the capacitance of the charge storage device, which is critical for maintaining a logic state dynamically, to be maintained and scaled proportionately with the decrease in processing dimensions. Processing improvements as described above are only one area in which DRAM technology has been improved. In order to fully utilize the improvements in processing, improvements in design techniques, such as DRAM architectures, have also occurred.
Existing DRAM architectures typically feature memory arrays evenly distributed around a centrally located control logic. The centrally located control logic generates critical timing control signals that selectively activate a predetermined portion of the memory for the purpose of reading and writing data to a predetermined memory location. A primary problem with this architecture is an inherent time delay of the critical timing control signals which need to be routed a significant distance from the centrally located control logic to the furthest removed memory cells. The problem associated with having a centrally located control logic is a problem associated with the critical timing control signals being skewed from one another throughout the different portions of the die. Some of the effects of having the critical timing signals skewed throughout the different portions of the die include, but are not limited to, causing word line drivers to malfunction when accessing a row of DRAM bit cells within the DRAM array, and producing control signals at a point in time which biases transistors in a destructive manner. In general, these effects resulting from the memory architecture reduce the overall performance and reliability of a DRAM circuit.